Latest Advances in Cadence IC Packaging Technology Further Tighten Design Cycle; New Allegro Technology Improves Productivity and High-Frequency Accuracy With Unified Design Flow to Address Complex Packaging Needs
SAN JOSE, Calif.—(BUSINESS WIRE)—Aug. 22, 2005—
Cadence Design Systems, Inc. (NYSE:CDN) (Nasdaq:CDN)
today announced the latest advances in its IC packaging technology,
slated to improve productivity and accuracy for shorter design cycle
time. The Cadence(R) Allegro(R) system interconnect design platform
has been enhanced with improvements in the Cadence constraint-driven
IC Packaging co-design flow and enhanced power and signal integrity
(SI) analysis accuracy.
As IC packaging technology continues to change rapidly, its
importance as a critical link in the silicon-package-board design flow
grows. This precipitates the need for strong capabilities to address
current and future packaging technologies such as wirebond, perimeter
array flip-chip, full array flip-chip, and stacked multi-die packages.
"These latest advances in Cadence IC packaging technology provide
Amkor and our design customers with significant opportunities for
savings in design cycle time while maintaining and improving overall
quality," said Steven Lowder, Amkor's vice president of World Wide
Design. "As a leading provider of packaging and test solutions for
complex multi-die designs, Amkor and our customers benefit from the
Cadence commitment to enabling IC package co-design and analysis."
This new Cadence IC packaging technology, part of the latest
Allegro release, improves accuracy for advanced package modeling with
an easy-to-use, unified design flow for faster creation of complex
package models. With the Cadence IC packaging solution, complex
packages are modeled by solving for 3D structures and generating
multi-port S-parameter models that are accurate up to 4 GHz. This
embedded 3D field solver approach also provides faster model creation
compared to the traditional approach of loosely integrated point
tools.
"These latest advances in Cadence IC packaging technology provides
us with impressive savings in design time," said Kevin Roselle, CTO of
Bayside Design Inc. "As we move into the next era of packaging, this
kind of support from our design automation software partners is
extremely important, especially in the area of power delivery design
and analysis."
As part of the latest TSMC Reference Flow 6.0, the Allegro Package
Designer provides an integrated power integrity verification flow with
VoltageStorm(R) Dynamic Gate power analysis so that IC core dynamic IR
drop in the chip can be predicted, including package load effects.
Integration creates models of the package PWR/GND structures, which
map directly to the IC Bump ports and create a complete
package-silicon PWR/GND network for verification. The
Allegro-VoltageStorm integration automates the flow, eliminating
error-prone manual model generation and mapping.
"Dynamic IR drop is a major concern for both chip and package
design," said Edward Wan, senior director of design service marketing
at TSMC. "Without package IR loading, high-speed digital designers may
have incomplete dynamic IR drop margins that severely reduce chip
performance. Reference Flow 6.0 incorporates the Allegro Package
Designer's integrated flow that helps designers simultaneously
evaluate these effects in an automated and efficient manner."
"These additions to our production proven IC packaging technology
extend our leadership in this important market," said Jamie Metcalfe,
vice president of marketing for IC Packaging Co-design products at
Cadence. "We continue to focus our technological development on
simplifying the design process and helping manufacturers design
products for fast volume production."
Productivity and ease-of-use improvements include wirebond design
reuse, which provides the ability to reuse complex wirebond tiers in
different designs. The addition of a Microsoft Excel interface for I/O
planning data completes the offering.
About Cadence
Cadence enables global electronic-design innovation and plays an
essential role in the creation of today's integrated circuits and
electronics. Customers use Cadence software and hardware,
methodologies, and services to design and verify advanced
semiconductors, printed circuit boards and systems used in consumer
electronics, networking and telecommunications equipment, and computer
systems. Cadence reported 2004 revenues of approximately $1.2 billion,
and has approximately 5,000 employees. The company is headquartered in
San Jose, Calif., with sales offices, design centers, and research
facilities around the world to serve the global electronics industry.
More information about the company, its products, and services is
available at www.cadence.com.
Cadence, the Cadence logo, Allegro and VoltageStorm are registered
trademarks of Cadence Design Systems, Inc. All other trademarks are
the property of their respective owners.
Contact:
Cadence Design Systems, Inc.
Judy Erkanat, 408-894-2302
Email Contact
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